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| Preliminary FM573/574 Nonvolatile Octal Latch/Register Features 8-bit Nonvolatile Latch * Logic state is preserved in the absence of power * Over 10 Billion (1010 ) nonvolatile state changes * Advanced high-reliability ferroelectric process Operates like conventional CMOS logic * Transparent (573) or D-Flip-flop (574) operation * FM573 transparent for C high, latched for C low * FM574 data is clocked on the rising edge of C * 33/80 ns data propagation delay (5V/3V) * 30 MHz/12 MHz Maximum frequency (5V/3V) Automatic Nonvolatile Operation * Latched state is stored automatically * State is automatically restored on power-up * Power supply monitor prevents low-VDD writes Low Power Operation * Supply voltage of 2.7V to 5.5V * 125 A standby current Industry Standard Configuration * Industrial temperature -40 C to +85 C * 20-pin SOP or DIP Description The FM573 and FM574 are innovative circuits that store inputs like conventional logic families, and then retain the stored state in the absence of power. These products solve three basic problems in an elegant fashion. First, they provide continuous access to nonvolatile system settings without performing a memory read operation or using dedicated processor I/O pins. Second, they allow the storage of signals or data that may change frequently and possibly without notice. Third, they allow the nonvolatile storage of a few bits of data or system settings without the system overhead and extra pins of a serial memory. The FM573 is a transparent latch. The inputs are passed to the outputs when the clock is high; the state is latched when the clock goes low. The FM574 is a Dtype register. Inputs are stored and passed to the outputs on the rising edge of the clock. The nonvolatile latch is a unique product that serves a variety of applications. A few ideas as follows: u Controls relays and valves with automatic setting on power-up without processor intervention. u Interface to soft/momentary front-panel switches and indicator lamps. Capture switch settings and light LED's without processor intervention. u Replaces jumpers & control signal routing u Initialize state of I/O card signals. u Save system errors or status codes when power fails with a fast, no overhead write and automatic restore on power up. u Eliminate the overhead of serial memory for systems needing only a few bits of data. The FM573 and FM574 are provided in a 20-pin DIP or SOP. They are rated from -40C to +85C. This data sheet contains specifications for a product under development. Characterization is not complete; specifications may change without notice. Pin Configuration OE D0 D1 D2 D3 D4 D5 D6 D7 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 C Pin Names D0-D7 Q0-Q7 C /OE VSS VDD Function Data in Data Out Clock/Latch Enable Output enable Ground Supply Voltage Ordering Information FM573-P FM573-S FM574-P FM574-S Transparent latch, 20-pin plastic DIP Transparent latch, 20-pin SOP Register, 20-pin plastic DIP Register, 20-pin SOP Other package types may be available. Contact the factory for more information. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058 27 March 2001 www.ramtron.com 1/10 Ramtron Figure 1. Block Diagram Mux FM573/574 Dn S1 S2 D D Q Qn OE Q Mux C S1 S2 D Nonvolatile section Power-up Restore State Change Detect Nonvolatile Latch Q D L VDD Power Monitor Q Reference Pin Description Pin Name /OE C D0-D7 Q0-Q7 VSS VDD Pin Number 1 11 2-9 12-19 10 20 I/O I I I O I I Pin Description Output enable. When low, the outputs are driven. When high, the outputs are tri-stated. Controls the latching of data according to the truth tables below. Data in. Data out. Ground Supply Voltage Functional Tables FM573 Table /OE 1 0 0 1 X 0 1 1 C Dn X X Dn Dn Internal Qn X Qn Dn Dn Output Qn Hi-Z Qn Dn Hi-Z Description Tri-state outputs Outputs enabled, hold state Transparent Load data, outputs tri-state FM574 Table /OE 1 0 0 1 X X C Dn X X Dn Dn Internal Qn X Qn Dn Dn Output Qn Hi-Z Qn Dn Hi-Z Description Tri-state outputs Outputs enabled, hold state Load data, outputs enabled Load data, outputs tri-state 27 March 2001 2/10 Ramtron FM573/574 This power up sequence occurs as follows. On detection of a power-up, the internal nonvolatile latch is read. This value is then placed on an internal version of the Dn input. A single internal clock is generated to cause the user latch to accept the restored data. After this process is comp lete, the latch provides normal user-controlled operation. Users should not attempt to latch externally supplied data prior to tPUH after VDD reaches VMIN. The following diagram illustrates the power-up and down sequences. Figure 2. Power Cycle Flow Chart Overview Nonvolatile logic is a revolutionary product family that simplifies the design of system control functions. The FM573 is a transparent octal latch; the FM574 is an octal D-type register. These products are unique because the stored values also are retained in the absence of power. They are pin and functionally compatible with their industry standard CMOS equivalents. Any change in the latched state automatically is written into a nonvolatile ferroelectric latch. This function is possible due to the fast write time and extremely high write endurance of the underlying ferroelectric memory technology. A new state becomes nonvolatile no more than 500 ns (VDD=5V) after the write begins. Users interface to a conventional latch rather than directly to the nonvolatile latch. Equivalent ferroelectric nonvolatile latches shadow the user's latches. They offer a very high but not unlimited number of write-cycles. Therefore, the internal state machine writes to the nonvolatile latch only if the latched state has changed in order to minimize the actual number of nonvolatile write-cycles. This determination is made independently for each bit. Due to the short write-time and realistic power slew rates, it is virtually impossible for the system to lose power before the nonvolatile state is acquired. Power Down Sequence An internal power monitor blocks updates to the nonvolatile latch when VDD is below V (internal MIN voltage reference). The power supply monitor also blocks write access to the user latch when VDD is below V . To guarantee a proper nonvolatile write MIN of the last value, state changes should cease tPDS before VDD reaches VMIN. The VMIN threshold is low enough that no special action may be needed in systems with slow slew rates. For fast power supply slew-rates or for systems that run down to relatively low supply voltages, the user should employ some form of low-VDD reset that trips above VMIN. Power Up The VMIN threshold is a critical parameter for several aspects of product operations. On power-up, the FM573/574 automatically restores the Qn outputs (and internal latches) to the previously stored state. This process begins as VDD rises to V MIN and is completed tRES afterward. Thus for all practical purposes, the nonvolatile values have been restored as soon as the system logic is functional on powerup. After the restore process, the latch is indistinguishable from its last state prior to power down and operates normally. System VDD rises, bandgap begins to function No No VDD > VMIN? VDD < VMIN Yes Yes Read nonvolatile store Complete NVwrites in progress No Block new writes to NV-Latch, user latch Read complete? Yes Restore data to user latch, drive pins No Restore complete? Yes Allow user access to latch, normal operation 27 March 2001 3/10 Ramtron FM573/574 power is lost, the nonvolatile shadow-latches retain the last latched state. On power up, the ferroelectric latches are read. The outputs of these latches will be placed on the internal Dn inputs. The power control circuit will then cause the internal `C' signal to go high. This rising edge passes the nonvolatile value instead of the external input into the user register. The internal Clock will then be released and the nonvolatile value will be stored into the user register. This entire restore process takes tRES from VDD > VMIN. After the restored nonvolatile value is loaded into the user register, normal operation begins. The first user write should occur t PUH after VDD > VMIN. Functional Description - FM573 The FM573 is an octal transparent latch. The Qn outputs track the Dn inputs while the Clock C signal is logic 1. When the C signal goes to logic 0, the Dn inputs are latched. In this aspect, the FM573 operates identically to a conventional latch of the same type. As shown above, it has the same functional truth table as an ordinary 573-type product. The FM573 is unique in its behavior during power up and power down. It also is unique in providing behind the scenes intelligence to manage the storage of settings. Each latched state is compared to the stored nonvolatile state. Comparison is made for each individual bit. If any bit has changed from its stored value, the new bit value automatically is written to the corresponding nonvolatile ferroelectric latch. Only the changed bits are written. For the transparent version, unlatched changes on the Qn outputs are not written to nonvolatile storage. This operation continues as long as power is within tolerance (above VMIN). The nonvolatile circuit operates entirely in the background and has no operating impact. When power is lost, the nonvolatile shadow-latches retain the final latched state. On power up, the ferroelectric latches are read. The outputs of these latches will be placed on the internal Dn inputs. The power control circuit will then cause the internal `C' signal to go high. Rather than passing the inputs signal to the output in transparent fashion, it will pass the nonvolatile value instead. After satisfying the minimum high clock-time, the internal Clock is released and the nonvolatile value is loaded into the user latch. This entire restore process takes tRES from V > VMIN. After the restored nonvolatile DD value is loaded into the user latch, normal operation begins. The first user write should occur tPUH after VDD > VMIN. Applications The FM573/FM574 runs at a speed that is comparable to the industry standard HC family logic. However, the nonvolatile-write operations, while fast in nonvolatile memory terms, are slower. Therefore, the nonvolatile logic runs `behind' the user logic. Three practical scenarios are identified in this data sheet. One scenario that is not practical is to have rapidly changing states, at high speed, continuing indefinitely. For example, an address latch on a microprocessor bus is not feasible due to limited nonvolatile write endurance. First, a free running clock in the kHz (or less) range is applied to the FM574. In this application, the nonvolatile logic can keep pace with state changes and continue for relatively long periods to indefinitely depending on the clock frequency. Slow mechanisms such as relays and valves can be controlled, and front panel interfaces can be made. The second scenario is to employ an event driven clock. The host issues one clock or a high-speed burst as needed to an FM573 or FM574. In the case of a high speed burst, the nonvolatile logic may get behind, but will catch up when the burst is completed. A special variation is to connect the clock input to a power-down reset device. This circuit captures a snapshot of the inputs on power-down. In this application, care must be taken in the system design to avoid capturing the inputs on power-up and thereby losing the old setting. A clock that is either software generated or controlled by other logic may be used as well. The third scenario is to monitor a continuous data stream and to hold it when an event occurs. This is analogous to a nonvolatile track-and-hold function. For this case, the hold signal is applied to an FM573. Diagrams of these applications are shown below. Functional Description - FM574 The FM574 is an octal D -register. Its behavior is similar to the FM573 except that Qn outputs do not change until the rising edge of the Clock. On the rising edge of the clock signal, the inputs are loaded and passed to the Qn outputs. In this aspect, the FM574 operates identically to a conventional latch of the same type. The latched state is compared to the stored nonvolatile state for each bit. If any bit has changed from its stored value, the new value automatically is written to the nonvolatile ferroelectric latch. This operation continues as long as power is within tolerance. The nonvolatile circuit operates entirely in the background and has no operating impact. When 27 March 2001 4/10 Ramtron Figure 3. Applications FM573/574 kHz Control & Monitoring Power-fail & Watchdog Reset Event Capture a1 a2 a3 a4 a1 a2 a3 a4 VDD1 b1 b2 b3 b4 b1 b2 b3 b4 D0 FM574 Q0 Relay Relay FM574 D0 Q0 MCU D7 Q7 GND Microprocessor Timer output = 1 kHz FM574 Q0 D0 D7 Q7 RST Dog Selector Q7 D7 1 2 3 1232 PB TD TOL 8 VDD ST RST RST 7 6 5 GND 4 FM574 Timing VDD 4.5V 2.5V 2.0V 4.5V 2.5V 2.0V RST Nonvolatile Track & Hold Joystick A/D A1 A2 A3 A4 DAC 1 DAC 2 D0-73 D0 FM573 Q0 8 D7 Q7 To Controller Hold This figure is a conceptual illustration of different modes of operation, not a complete circuit design. 27 March 2001 5/10 Ramtron FM573/574 Electrical Specifications Absolute Maximum Ratings Description Ambient storage or operating temperature Voltage on any pin with respect to ground D.C. output current on any pin Lead temperature (Soldering, 10 seconds) Ratings -40C to + 85C -1.0V to +7.0V TBD 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified Symbol Parameter Min Typ Max Units VDD Main Power Supply 2.7 5.5 V VMIN State change blocked/restored 2.40 2.5 2.54 V ISB Quiescent Supply Current 125 A IDDDY Dynamic Supply Current 20pF*V*f*n A ex. 3.3V, 10 MHz, 8 inputs 5.28 mA IDDNV State Change Supply Current 500 A ILI Input Leakage Current 10 A ILO Output Leakage Current 10 A VIL Input Low Voltage -0.3 0.3*VDD V VIH Input High Voltage 0.7*VDD VDD + 0.5 V VOH Output High Voltage V @ IOH = -8 mA VDD>4V VDD-0.8 @ IOH = -8 mA VDD<4V VDD-1.0 VOL Output Low Voltage 0.8 V @ IOL = 8 mA Notes 1 1,8 2 3,4,5 5 6 6 1 1 1,7 1,7 Notes 1. Referenced to VSS. 2. C = VSS, all other inputs at VDD or VSS 3. Dynamic supply current depends on the clock frequency, the frequency of inputs toggling, and the number of bits toggling. In the formula, V = VDD; f is clock frequency; n is the number of bits switching. The Dn inputs toggle at approximately a 50% duty-cycle at 1/2 of the frequency of C and comply with the minimum setup time. Outputs are tri-stated. All input levels at VDD and VSS. If C is static but the inputs toggle (573 in transparent mode), then the f should be the frequency of the inputs. 4. In a realistic system, the IDD needed to drive the loads also should be considered. IL = CL *V*fo *n where CL is the load capacitance, V is the output swing voltage, fo is the output frequency, and n is the number of bits switching. 5. Changes in state cause a nonvolatile write which adds a DC current component to the static power or dynamic for the duration of the nonvolatile write operation. The total current consumption after each state change = ISB + IDDNV + IDDDY . After the state change is recorded, total current consumption = ISB + IDDDY. 6. VIN or VOUT = VSS to VDD 7. This parameter is characterized but not tested. 8. All state changes will be ignored when VDD is below VMIN. VDD rising above VMIN causes the user latch to be restored from the nonvolatile latch. 27 March 2001 6/10 Ramtron AC Parameters TA = -40 C to + 85 C, CL = 50 pF unless otherwise specified VDD=2.7V - 3.6V VDD=5.0V +/- 10% Symbol Parameter Min Max Min Max fMAX Maximum clock frequency 12 30 tCW Clock minimum pulse width 30 8 tPD Propagation delay Dn to Qn 80 33 Propagation delay C to Qn tEN Output enable time /OE to Qn 70 28 tDIS Output disable /OE to Qn Hi-Z 60 25 tDS Data setup Dn to C low (573) 5 5 Data setup Dn to C (574) tDH Data hold Dn after C low (573) 7 5 Data hold after C high (574) Notes: 1 This parameter is characterized but not tested. FM573/574 Units MHz ns ns ns ns ns ns Notes 1 Power Cycling and Data Retention TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified VDD=2.7V - 3.6V VDD=5.0V +/- 10% Symbol Parameter Min Max Min Max Units Notes Nonvolatile data retention 1 1 Year 1 Latched state changes 1E10 1E10 Changes 2 tPDS Last state change to VMIN 2 1 3 S tRES VMIN to output valid 1 1 4 S tPUH VMIN to first user write 1.5 1.5 4,5 S Notes: 1. Data retention is measured from the last state change, and is the time that a state will be retained at 85 C and correctly restored on power-up. The process of powering up (and reading the nonvolatile state) refreshes the stored state and re-starts the data retention period even if the state is unchanged. 2. The nonvolatile elements are written when the latched state changes. Changes on either Dn or Qn that are not latched have no effect. 3. The last write to the nonvolatile latch element must occur prior to reaching VMIN during a power down. 4. After the power supply reaches approximately V during a power up, the nonvolatile latch is read and the MIN value restored to the user latch. This spec. provides the time needed to restore the FM573/FM574 pins to the restored state depending on the state of /OE. 5. The user should not attempt to write during the restore process. In particular, powering up in transparent mode (FM573) defeats the purpose of using a nonvolatile latch. Capacitance TA = 25 C , f=1.0 MHz, VDD = 5V Symbol Parameter Max CIN Input capacitance 6 Notes 1 This parameter is characterized but not tested. AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Units pF Notes 1 Equivalent AC Load Circuit 1.3V 0.1VDD to 0.9VDD 10 ns 0.3VDD, 0.7 VDD 3300 Output 50 pF 27 March 2001 7/10 Ramtron FM573 Timing tCW 1/fMAX FM573/574 C tDS tDH Dn D1 tPD D2 tPD Qn old tEN D1 D2 tDIS OE FM574 Timing 1/fMAX tCW C tDS tDH Dn D1 tPD old Qn tEN D1 tDIS OE Power Cycle Timing (574-timing shown) C D0 D1 DLAST ~ ~ D0 D1 Dn ~ ~ Qn Q0 Q1 QLAST QLAST Q0 Q1 ~ ~ tPDS VDD VMIN tRES VMIN ~ ~ tPUH 27 March 2001 8/10 Ramtron 20-pin SOP FM573/574 Index Area E H Pin 1 D A B A1 .10 mm .004 in. h 45 L C e Controlling dimensions is in millimeters. Conversions to inches are not exact. Symbol Dim Min Nom. Max A mm 2.35 2.65 in. 0.0926 0.1043 A1 mm 0.10 0.30 in. 0.004 0.0118 B mm 0.33 0.51 in. 0.013 0.020 C mm 0.23 0.32 in. 0.0091 0.0125 D mm 12.6 13.0 in. 0.4961 0.5118 E mm 7.40 7.60 in. 0.2914 0.2992 e mm 1.27 BSC in. 0.050 BSC H mm 10.00 10.65 in. 0.394 0.419 h mm 0.25 0.75 in. 0.010 0.029 L mm .40 1.27 in. 0.016 0.050 0 8 27 March 2001 9/10 Ramtron 20-pin DIP FM573/574 E1 Index Area D A2 A1 D1 A eA eB E e b B1 Controlling dimensions is in inches. Conversions to millimeters are not exact. Symbol Dim Min Nom. Max A in. .140 .190 mm 3.56 4.83 A1 in. .015 .060 mm .381 1.52 A2 in. .120 .140 mm 3.05 3.56 B in. .015 .020 mm .381 .508 B2 in. .055 .065 mm 1.40 1.65 D in. .970 1.04 mm 24.64 26.42 E in. .280 .325 mm 7.11 8.26 E1 in. .250 .270 mm 6.35 6.86 e in. .090 .100 .110 mm 2.29 2.54 2.79 eA in. .300 BSC mm 7.62 BSC eB in. .310 .385 mm 7.87 9.78 27 March 2001 10/10 |
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